This is a specification for Q, an instruction set architecture (ISA) for a parallel processing system supporting stream-based hybrid dataflow, such as MagicEight[6]1.This architecture is motivated primarily by a need for flexible and scalable parallel media processing. Other motivations include supporting specialized processors, capable of executing a restricted set of algorithms much more efficiently than a general purpose processor, and a decoupled memory access mechanism.
Q is an attempt to define an architecture that leverages the properties of dataflow machines to support parallelism, while retaining the advantages of sequential machines when executing singly. The programming model proposed minimizes the synchronization costs by synchronizing blocks of operations upon blocks of data, and allowing the size of the data blocks to be decided at runtime to match the available machine granularity.
In order to aid the task of describing the Q ISA, a virtual machine implementing the architecture will be presented, along with an architectural overview. The program elements are each described in depth, followed by an example program using Q program elements and its evaluation in Section 6. Another approach to describing the instruction set, without the use of a virtual machine, may be found in Section 7. A programming language for describing algorithms using elements of the Q instruction set is described in an appendix.