Another set of systems examined were those which used specialized processors connected in a dedicated pipe architecture. While evolved from the traditional graphics pipeline, these systems are generally capable of limited video processing, viewing the pixel rasters as texture mapped polygons.
The Silicon Graphics Infinite Reality graphics subsystem [23] [24] was designed for a different market than the other systems assesed: one in which performance is more important than cost. The Infinite Reality is a second generation of the Reality Engine architecture [25], which not only takes advantage of technological improvements but also increases the range of scalability.
The Infinite Reality is available on the Onyx2 workstations [26]. These systems contain from 1 to 24 MIPS R10K processors, each with 512 Kbits of primary inst. cache, 512 Kbits of primary data cache, and 32 Mbits of secondary cache. The main system memory is configurable from 512 Mbits up to 64 Gbits. From one to eight rendering pipelines are available on a workstation. Each rendering pipeline contains four Geometry Engines, and may be configured with one to four Raster Managers. From two to eight display ``channels'' may be provided per graphics pipeline, each generating an RGB signal at up to 1920x1200 60 fps non-interlaced.
The Geometry Engines (GE) are the subsystems responsible for performing polygon-to-triangle decomposition, geometry transformations and screen space projection. Other functions subsumed by the GE is image manipulation: rotations, warps, interpolation, decimation, filtering, and statistics measurement. Each GE utilizes a custom processor consisting of three SIMD processing elements, consisting of a dedicated register file and a floating point multiplier and arithmetic unit. The processing elements share a common multi-port SRAM, and all GEs in a system share a 2.9 Gb/s interface to main system memory. The processor operates at 90 MHz, and is controlled using a 195b micro-instruction. The micro-instructions are compressed, yielding average 2.7:1 reduction in size with minimal (1.5%) performance impact [24].
The transformed and projected triangles must be distributed to the appropriate Raster Manager (which use image space subdivision to provide parallelism.) This is done using a shared 3.2 Gb/s linear interconnect, the Triangle bus.
From one to four Raster Manager boards perform the triangle scan conversion, texture mapping, and rasterization. A single copy of the texture memory is stored on each Raster Manager board. Using 128 SDRAM devices (2048b wide) provides a texture read bandwidth of around 15 Gb/s per board and a total texture capacity of 128 - 512 Mb. The frame buffer memory is distributed for maximum read/write bandwidth: up to 320 rasterizing processors are used, each connected to a dedicated 256Kx32b SGRAM. The peak frame buffer access rates are in excess of 600 Gb/s.
| Chromatics Mpact2 | Talisman Escalante | GLINT & PerMedia | Infinite Reality | Units | |
|---|---|---|---|---|---|
| Geometry | 1 | 0.8 | 1.0 | 11 | MTriangles/sec |
| Rasterizing | 10 | 150 | 30 | 780 | MPixels/sec |
A number of integrated 3D graphics pipelines have appeared recently. One architecture is the Permedia (rasterizer) & GLINT Delta (triangle setup) combination from 3Dlabs [27], of which the Texas Instruments TVP4010 [28] is a licensed implementation.
My favorite, however, would have to be the Nintendo64. It contains an 94MHz R4200 processor, coupled with a dedicated graphics pipeline (the Reality Co-processor) from Silicon Graphics. Using two Rambus RDRAMs (32 Mb total) for memory, the Reality Co-processor renders 30 fps at a resolution of 640x480 using perspective projection, z-buffering, multi-resolution texture (MIP) mapping, environment mapping, and a form of anti-aliasing. And all at a price point of $200/complete system.