## 8/27/96 K. Ling-Pei Kung
## This file is created to facilitate compilation of vhdl sourc codes
## and generation of bit file.  
## You need to change some of the variable assignment

## enter the name of the ORCA chip you want to program
## and the top level vhdl source file (without the .vhd extension)

CHIP_NAME = boswell
DESIGN_NAME = top

## enter the vhdl design source directory and design files
SOURCE_DIR = src
VHDL_SOURCE = ${SOURCE_DIR}/top.vhd ${SOURCE_DIR}/counter_8b.vhd 

## This is the directory the analyzed design files will be stored
ANALYZED_DIR = work

## Synopsys design compiler unix shell command
DC = /usr/synopsys/hp700/syn/bin/dc_shell_exec -r ${SYNOPSYS}
## Script file for design compiler, don't forget the change the
## the name of the design in the script file.
DC_SCRIPT = dc.script

## Synopsys format for design
DESIGN_DB = ${DESIGN_NAME}.db

## EDIF format to be used by Foundary tools
DESIGN_EDIF = ${DESIGN_NAME}.edn

## Place and Route preference file, you specify the pin assignment here
PIN_ASSIGNMENT = /tmp_mnt/mas/disks/cheops/hdwe/p2/statemch/ORCA/template/${CHIP_NAME}/pin1_0.prf

## Utility program for hp700 to strip header information from bit file generated
## the bitgen program.

LODGEN = /tmp_mnt/mas/disks/cheops/hdwe/p2/statemch/ORCA/utils/lodgen_hp700

MAPPED = mapped.mrp mapped.ngd mapped.ngm mapped.ngo mapped.ncd
ROUTED = routed.drc routed.dly routed.par routed.pad routed.ncd
BITGENED = target.drc target.bgn target.bit target.lod 
LOG  = command.log view_command.log

target: target.lod

target.lod: target.bit
	${LODGEN} target.bit target.lod

target.bit: routed.ncd
	bitgen routed.ncd -w target.bit

mapped.ncd: ${DESIGN_EDIF}
	mapped.msc

routed.ncd: mapped.ncd
	par -l 3 -e 1 mapped.ncd -w routed.ncd ${PIN_ASSIGNMENT}

top.edn: ${VHDL_SOURCE}
	${DC} -f ${DC_SCRIPT}

clean:
	rm -f ${DESIGN_DB} ${DESIGN_EDIF} ${MAPPED} ${ROUTED} ${BITGENED} ${LOG}