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Last updated by Mark Lee on 06/19/97
This page contains information on State Machine hardware and low-level software. It is meant for people debugging the State Machine, and for those who wish to know more details about how it was designed.
The following is a discussion of the major components of the State Machine. It is divided into processing elements, storage elements, and interconnection elements.
The PowerPC 603 is a RISC, 32-bit addressed, 64/32bit databus low-power consumption, superscalar microprocessor.
The 603 has five separate execution units:
The IU executes most integer instructions in one clock cycle. The FPU is pipelined in order to allow one FP instruction to be issued each clock cycle. The BPU attempts to predict conditional branch statements, often achieving zero-cycle branches. The LSU is used to execute all load and store instructions while the SRU is used to manage system-level instructions.
The 603 provides instruction and data caching using 8-kbyte, two-way set-associative, physically addressed caches. These caches contain 64-entry, two-way set-associative, Data and Instruction Translation Lookaside Buffers (DTLB and ITLB) that provide address and block translation (used so that app code can all be compiled with an effective address starting with 0).
The 603 is also capable of issuing and retiring as many as three instructions per clock cycle. Out of order execution, used to increase performance, while maintaining all data dependencies is also supported by the 603.
In addition, the 603 features four power-saving modes: Nap, Doze, Sleep, and Dynamic. The Dynamic Power Management (DPM) of the 603 automatically powers up and down the separate execution units based on the instruction stream. Since CMOS circuits consume the most power on the clock edge, the DPM basically suppresses the clock until the execution unit is needed. The table below gives a summary for each of the four power-saving modes.
Table 1: PowerPC 603 Power Modes ------------------------------------------------------------------------ | Power Mode | Functional Units | Activation | Full-Power Wake Up | | | | Method | Method | ------------------------------------------------------------------------ | Full Power | All units active | N/A | N/A | ------------------------------------------------------------------------ | Dynamic | Requested logic | By | N/A | | (DPM) | by demand | instruction | | | | | dispatch | | ------------------------------------------------------------------------ | Doze | -Bus snooping | Controlled | -External asynchronous | | | -Data cache as | by sw | interrupts | | | needed | | -Decrementer interrupt | | | -Decrementer | | -Reset | | | timer | | | ------------------------------------------------------------------------ | Nap | Decrementer | Controlled | -External asynchronous | | | timer | by hw & sw | interrupts | | | | | -Decrementer interrupt | | | | | -Reset | ------------------------------------------------------------------------ | Sleep | None | Controlled | -External asynchronous | | | | by hw & sw | interrupts | | | | | -Reset | ------------------------------------------------------------------------
The reconfigurable logic of the State Machine board will be realized by a pair of AT&T 2c40 ORCA FPGAs. These FPGAs represent the state of the art in FPGAs at the time of the board construction. This model is fabricated with a 0.5 um CMOS process technology with 40,000 logic gates. In addition, they have low power consumption and high-frequency system clock operation (33Mhz-80Mhz).
As mentioned above, inside of each PLC is a Programmable Function Unit (PFU) and routing resources. All PLCs are identical, each containing four Look-Up Tables (LUTs) and four latches/flip-flops to implement different logic functions. The LUTs are SRAM and can be configured to operate in one of three modes: Combinatorial logic mode, ripple mode, and memory mode. The four latches/FFs can be configured to be positive or negative level sensitive latches, or positive or negative edge-triggered flip-flops. It can take input from either directly from PFU input or from the LUT. The flip-flops themselves can operate in different modes to realize synchronous/asynchronous, inverted/noninverted, or purely combinatorial logic. In addition, to speed up signals which feed external logic, the outputs of the FFs can be fed directly to the I/O pads for each PLC that is adjacent to a PIC.
A discussion of the routing resources of the ORCA can be divided into intra-PLC and inter-PLC routing. Intra-PLC routing resources are used to connect the inputs and outputs of the PFU to and from the inputs and outputs of the PLC. Inter-PLC routing resources are used to route between PLCs. To accomplish this, the R-nodes occur in groups of four: x1 (spans one PLC), x4 (spans four PLCs), xH (spans half the length/heighth of a PLC Array), and xL (spans the full length/heighth of a PLC Array). For each PLC there are sixteen x1 R-nodes (8 vertical, 8 horizontal), four sets of four x4 R-nodes, eight xH R-nodes (4 vertical, 4 horizontal), and eight xL R-nodes (4 vertical, 4 horizontal).
A subset of inter-PLC routing resources are the Clock R-Nodes. These dedicated clock R-nodes are used to provide a fast and low-skew clock (or other global routing). They run the entire length of the PLC array. There are two horizontal/vertical R-nodes per row/column.
Provide information about the FPGA modes of operation here.
The PowerPC 603 memory space is a mapping of external devices to specified address values. The devices are mapped so that by reading or writing to the address space of a device selects the device. This can be done because in hardware, ten of the twelve high order address bits are wired to logic controlling the chip enables of the devices. The PowerPC 603 Memory Space is given in Figure 1 below.
Figure 1: PowerPC 603 Memory Space
^ ^
| |
-----------|--------------------|
0x0000_0000| XXXXXXXXXXXXXXXXXX | X = Unused Memory Space
0x000F_FFFF| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x0010_0000| Page 0 SRAM |
0x001F_FFFF| |
-----------|--------------------|
0x0020_0000| Boswell SRAM |
0x002F_FFFF| |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x0040_0000| Johnson SRAM |
0x004F_FFFF| |
-----------|--------------------|
0x0080_0000| Register Interface |
0x008F_FFFF| Address Space |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x0100_0000| Boswell ORCA |
0x010F_FFFF| |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x0200_0000| Johnson ORCA |
0x020F_FFFF| |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x0400_0000| Boswell LUT Memory |
0x040F_FFFF| |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x0800_0000| Johnson LUT Memory |
0x080F_0000| |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x1000_0000| Boswell Interrupt |
0x1000_0001| Acknowledge |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0x2000_0000| Johnson Interrupt |
0x2000_0001| Acknowledge |
-----------|--------------------|
| XXXXXXXXXXXXXXXXXX |
-----------|--------------------|
0xFFF0_0000| PowerPC 603 | -> Aliased to exception table
0xFFF0_2FFF| Exception Table | in Page 0 memory
-----------|--------------------|
| |
| |
^ ^
One important note is how these bits are actually mapped to the pins of the PowerPC 603. For example, the address range 0x0010_0000 to 0x001F_0000 is used to select the Boswell SRAM. This means that address bit 10 of the PowerPC 603 is wired to the Boswell SRAM CE (chip enable) signal (The pin actually goes through a transceiver, gets renamed to BMCE, is used as an input to the Boswell SRAM PAL, and after some logic is perform, the appropriate CE pin on the Boswell SRAM is deasserted). 0x0010_0000 is mapped to address bit 10 because the MSB of the address is mapped to address bit 0. Table 2 gives a mapping of the device to the address bit that results from using this convention.
Table 2: Device to Pin Mapping ------------------------------------------------------------ | Device/Signal | PowerPC | PowerPC pin | Name at | | | address bit | name/number | device | ------------------------------------------------------------ | Boswell SRAM | A10 | PG1B | BMCE | ------------------------------------------------------------ | Johnson SRAM | A09 | PG2B | JMCE | ------------------------------------------------------------ | Boswell ORCA | A07 | BORCAB | PTBCE | ------------------------------------------------------------ | Johnson ORCA | A06 | JORCAB | PTJCE | ------------------------------------------------------------ | Boswell LUT | A05 | BLUTB | BLUTBLE | ------------------------------------------------------------ | Johnson LUT | A04 | JLUTB | JLUTBLE | ------------------------------------------------------------ | Boswell Int Ack | A03 | BINTAACK | BINT_AACK | ------------------------------------------------------------ | Johnson Int Ack | A02 | JINTAACK | JINT_AACK | ------------------------------------------------------------
It is important to note that this type of implementation has implications for the programmer who is writing applications of the State Machine. This says that if he writes address space 0x0300_0000 through 0x030F_FFFF, then both Boswell and Johnson ORCAs will be selected even though the addresses written are undefined in the PowerPC 603 memory space. This implementation is currently being reviewed to determine if this is how devices will be controlled in Version 4 of the State Machine.
The Register Interface is an Erasable Programmable Logic Device (EPLD) with registers for board control and returning board status. It is accessible by both the i960 and the 603. The address space is described in Table 2 below, followed by a summary of each register.
Table 3 : Register Interface Address Space ------------------------------------------------------------------ | i960 | 603 | Meaning | | binary | binary | | | address | address | | ------------------------------------------------------------------ | 00000 | 00011 | State Register (read only) | ------------------------------------------------------------------ | 10001 | 10011 | General Purpose Register (read/write) | ------------------------------------------------------------------ | 01010 | 01011 | LPI Interrupt | ------------------------------------------------------------------ | 11011 | 11011 | LP to State Machine Interrupt | ------------------------------------------------------------------ | 00100 | 00111 | Bus Priority Register (write only) | ------------------------------------------------------------------ | 10101 | 10111 | Helper/Configuration Register (write only) | ------------------------------------------------------------------ | 01110 | 01111 | FPGA interrupt store | ------------------------------------------------------------------ | 11111 | 11111 | Page Register (write only) | ------------------------------------------------------------------
The State Register is readable by both the i960 and the 603, and returns status bits about the State Machine board. Table 4 gives a description of each bit in the State Register.
Table 4 : State Register ------------------------------------------------------ | Register Bit | Description | ------------------------------------------------------ | Q1 | Board Configuration Mode | ------------------------------------------------------ | Q2 | Board Start Mode | ------------------------------------------------------ | Q3 | Boswell Configuration Done Signal | ------------------------------------------------------ | Q4 | Boswell /INIT Signal | ------------------------------------------------------ | Q5 | Johnson Configuration Done Signal | ------------------------------------------------------ | Q6 | Johnson /INIT Signal | ------------------------------------------------------ | Q7 | Configuration Clock Enable | ------------------------------------------------------ | Q8 | Configuration Synchronization Clock | ------------------------------------------------------
Note that the board mode values in this register are read only. Bits Q1 and Q2, are mirrors of the writable Q4 and Q5 bits of the Bus Priority Register. The Boswell/Johnson /INIT signals are used to detect bit stream errors in the configuration data. The Boswell/Johnson Configuration Done signals indicate when configuration for the FPGAs have completed.The configuration clock is used by the ORCAs during configuration mode. The configuration sync signal (csync) is used to tell the bus controller when a new configuration byte may be written to the FPGA(s) (The ORCAs require that a new configuration byte must be written to the every eight configuration clock cycles.)
The LPI interrupt bit allows the State Machine to interrupt the i960. This has been designed to allow the 603 to notify the resource manager when a stream computation is complete.
The LP SMI interrupt bit allows the i960 to interrupt the 603 to request a service. Supported services are to run a 603 application in a specific application code slot, and to configure the Boswell and/or Johnson ORCA.
The Bus priority register is used by the bus controller during bus arbitration. Each of the priority bits determine which device may own the bus in the case when the bus is requested simultaneously by more than one device. In addition to priority bits, the board mode bits are also used by the bus controller. Table 5 gives a description of each bit in the Bus Priority Register.
Table 5 : Bus Priority Register ------------------------------------------------------ | Register Bit | Description | ------------------------------------------------------ | Q1 | Boswell Priority Bit (Boswell/603) | ------------------------------------------------------ | Q2 | Johnson Priority Bit (Johnson/603) | ------------------------------------------------------ | Q3 | PowerPC 603 Priority Bit (603/i960) | ------------------------------------------------------ | Q4 | Board Configuration Mode Bit | ------------------------------------------------------ | Q5 | Board Start Mode Bit | ------------------------------------------------------ | Q6 | i960 accessible /HRESET to 603 | ------------------------------------------------------ | Q7 | Unused | ------------------------------------------------------ | Q8 | Unused | ------------------------------------------------------
The Helper/Configuration Register holds bits which help control configuration of the FPGAs. In addition, the Boswell and Johnson LUT chip selects are on this register, but their outputs are enabled whenever the i960 is driving the 603 data bus (Bits Q4 and Q5 drive whenever the page register is driving). Table 6 below gives a description of each bit in this register.
Table 6 : Helper/Configuration Register ------------------------------------------------------ | Register Bit | Description | ------------------------------------------------------ | Q1 | ORCA Configuration Clock Enable Bit | ------------------------------------------------------ | Q2 | Boswell Configuration Start Bit | ------------------------------------------------------ | Q3 | Johnson Configuration Start Bit | ------------------------------------------------------ | Q4 | Boswell Look Up Table Chip Select | ------------------------------------------------------ | Q5 | Johnson Look Up Table Chip Select | ------------------------------------------------------ | Q6 | Configuration Master Bit | ------------------------------------------------------ | Q7 | Unused | ------------------------------------------------------ | Q8 | Unused | ------------------------------------------------------
The FPGA Interrupt Store Register stores the values of the Boswell and Johnson interrupts to the 603. When the 603 receives an external interrupt, this register is polled to discover which ORCA sent the interrupt. The mapping of the values are as follows:
Since the address bus of the i960 is only 16 bits wide and the PC6data bus is 23 bits wide, this register must drive the upper order address bits, providing a means of paging. In addition, this register allows i960 accesses to assert chip selects to certain devices. Table 7 below gives a description of each bit in this register.
Table 7 : Page Register ------------------------------------------------------ | Register Bit | Description | ------------------------------------------------------ | Q1 | Unused | ------------------------------------------------------ | Q2 | Boswell Select Bit | ------------------------------------------------------ | Q3 | Johnson Select Bit | ------------------------------------------------------ | Q4 | Page 0 SRAM Select | ------------------------------------------------------ | Q5 | PowerPC 603 Address Bus Bit 16 | ------------------------------------------------------ | Q6 | PowerPC 603 Address Bus Bit 17 | ------------------------------------------------------ | Q7 | PowerPC 603 Address Bus Bit 18 | ------------------------------------------------------ | Q8 | PowerPC 603 Address Bus Bit 19 | ------------------------------------------------------
The Page 0 SRAM holds both 603 code and ORCA configuration information. It is accessible by both the 603 and the i960. The 603 may access the SRAM in burst transfers which it typically uses in instruction cache line fills. The i960 writes the code and configuration information during WRITE board mode. The SRAM is partitioned by the 603 memory mapping facilities into 128 Kbyte slots as follows:
Figure 2 : Page 0 SRAM Memory Space ^ ^ | | -------|------------------| 0x00000| Exception Table | -------|------------------| 0x03000| Operating System | -------|------------------| 0x10000| Ramlog Header | |------------------| | Ramlog Space | -------|------------------| Base Address in 0x20000| Program Slot #1 | PowerPC 603 Address -------|------------------| Space: 0x40000| Program Slot #2 | 0x0010_0000 -------|------------------| 0x60000| Program Slot #3 | -------|------------------| 0x80000| Program Slot #4 | -------|------------------| 0xA0000| Program Slot #5 | -------|------------------| 0xC0000| FPGA Config | -------|- - - - - - - - - | 0xD0000| Data Slot #1 | -------|------------------| 0xE0000| FPGA Config | -------|- - - - - - - - - | 0xF0000| Data Slot #2 | -------|------------------| | | | | ^ ^
The Boswell and Johnson busses are symmetrical to each other and primarily connect each FPGA to its respective stream data SRAM. In addition, the Look Up Table SRAM may also be written by this bus. (This is to support programming from the i960 and the 603.) This bus also interfaces with the PC603 bus, and allows the PC603 to access the stream data SRAM and to configure the FPGA. Configuration and LUT programming from the i960 is also supported. Note that the Boswell and the Johnson address busses may drive each other when the two FPGAs are working in tandem.
The IntraFPGA bus is a 52-bit wide connection which directly connects the Boswell and Johnson ORCAs. This bus is meant to be used in Type II applications where the two ORCAs are working together to realize a single, large function.
The bus controller has two main functions, one of which is arbitration. The bus controller is responsible for arbitrating between bus masters for each of the three busses on the State Machine board. However, even though each bus may have two possible masters, the current state of the board may dictate that only certain transactions should be allowed. The startbit and config bit specify the board mode and is used to help the bus controller control ownership of the individual busses. The four board modes and the cooresponding bit mapping is given below in Table 8:
Table 8 : Board Modes
----------------------------------
| Mode Encoding | Mode |
| (startbit,config bit) | Name |
----------------------------------
| 0,0 | Idle |
----------------------------------
| 0,1 | Write |
----------------------------------
| 1,0 | Config |
----------------------------------
| 1,1 | Normal |
----------------------------------
During Idle mode, the State Machine initiates no activity. The only trasfers supported are i960 access to the Register Interface to change the board mode. This is the default mode of the State Machine after power-up and after a system reset. It ensures that the board initiates no activity until the P2 brings it out of Idle mode.
During Write mode, the i960 may write to registers on the Register Interface, write ot the Page 0 SRAM to download 603 code or ORCA conifguration code, and program both the Boswell and Johnson SRAM LUTs. This is the only mode in which the i960 has full access to the State Machine. The 603 is either in /HRESET or all of its transfers are stalled (Verify this).
During Configuration mode, the 603 is brought out of Hard Reset. This is the mode in which either the 603 or the i960 configures the FPGAs. If the i960 is the Configuration Master (as determined by a bit in Register Interface), then it has the same access privileges as in WRITE MODE. If it is not the Configuration Master, then it only has access to the Register Interface, and the Page 0 sram. If the 603 is the Configuration Master, then it has access to the Boswell and Johnson busses (Regardless of the value of the Configuration Master bit, the 603 has access to the Register Interface, and PAGE0 sram in this mode).
In Normal mode, the State Machine is in full operation. The 603 has full access to the 603 and Boswell/Johnson busses. The i960 only has access to the PAGE 0 Sram and Register Interface in this mode.
The 603's reset signal is dependent upon the mode, but is not completely determined by it. During IDLE MODE, the 603 is held in hard reset, and stays there until the board mode is switched to either CONFIG MODE or NORMAL MODE (whichever is done first). Optionally, the i960 may order the 603 into reset by writing to a bit in the register interface. In this case, the 603 remains in HRESET until this bit is deasserted, and the board mode is CONFIG or NORMAL MODE. (At this point, the 603 starts with the boot strap code.) This feature was added to allow the i960 software to reset the 603, without placing the board into IDLE Mode. It also allows the State Machine board to be used without the 603. (i.e. the FPGAs may work without the 603 intiating any bus transactions.)
ORCA FPGAs may be reset by not only the Cheops hard reset button, but also by writing to the configuration control bit in the register interface. Configuration starts when this bit is asserted low then released to high. By asserting and keeping this bit low, the FPGA may be held in reset. (Note that this automatically occurs when the Cheops sysreset button is hit.) This gives both the i960 and the 603 the ability to reset the FPGAs, and possibly hold them in reset.
TRANSFER CONTROL - Not ready for prime time
TRANSFER TYPES SUPPORTED
Transfer beats:
============================
R = single beat read
W = single beat write
R8 = 8-beat read
W8 = 8-beat write
NOTE: Transfer Sizes
For single beat transactions, 1,2,3,or 4 byte sized transactions are
supported for the 603. (Only 1-byte wide transfers are available for
the P2, since the Reg I/F is only 8 bits wide.) For Burst MOde (R8/W8)
word length (4 bytes wide) is assumed.
Note that the 603 is being used in reduced pinout mode, so the data bus is only
32 bits wide.
603 <--> pg0 (local) memory R/W, R8/W8
603 <--> Register Interface R/W
603 <--> Boswell/Johnson Memory R/W, R8/W8
603 <--> LUT W
603 <--> BosORCA R/W
ORCA <--> (Boswell/Johnson) Memory R/W
ORCA <-- LUT R
i960 <--> Page 0 MAR R/W
i960 <--> Register Interface R/W*
i960 <--> Boswell/Johnson ORCA R/W
* The i960 also has direct access to HRESET and the PC603 bus priority bits.
i.e. Writing to these bits does not require ownership of the PC603 bus.
Burst Transfers:
============================
The 603 is capable of burst mode transfers which it uses for cache line fills.
In this mode, the 603 negotiates for the address and data busses once for
eight beats of data transfer. The addresses must be generated external to the
603. For instruction fetches and other accesses to the Page 0 SRAM, the burst
mode counting is performed by the Page 0 Memory Address Register (MAR). This
MAR consists of address registers, as well an EPLD which performs the counting.
The MAR loads in the address generated by the 603, and the counter updates
the low order address bits during the burst transfer.
Similarly, the Boswell and Johnson busses are capable of burst mode transfers.
2-beat transfers:
============================
We decided not to support 2-beat transfers (which are only used for "a double-
word aligned load- or store-double operation to or from the floating-point
GPRs".
To cancel any 2-beat transactions that the 603 starts, we can assert /TEA which
will cause a machine check exception. (We also use this error if the 603 tries
to write to a Boswell/Johnson bus while the ORCA is asserting 'buslock' for
flood transactions.)
The conflict with floods should be rare since we have interrupts between the
ORCAs and the 603 to handshake. But if the 2-beat transfers are attempted,
we may hang the 603.
LOCAL PROCESSOR ADDRESS SPACE
----------------------------------------------------
O Data Alignment from i960 to State Machine
The State Machine has byte-wide bus transceivers (U64, U58) which align the 8-bit
data from the P2 into byte slots in the PC6_DATA bus. In order to be consistent with
the 603's convention of designating the slots in byte transfers, the following addressing
scheme is used:
addr
-------------------------------------------------
0b11 pc6_data<0..7> (least significant data)
0b10 pc6_data<8..15>
0b01 pc6_data<16..23>
0b00 pc6_data<24..31> (most significant)
The logic which implements this is in the Register Interface.
O Low Order Addressing to the Boswell and Johnson SRAM from the i960
When the 603 asserts lowest order address bits 0b11 for a byte-wide access, it aligns the byte in the lowest order data bus slot. This is opposite of what the i960 on the P2 does. (i.e. the i960 will assert low order address bits 0b00 for the same data byte slot.) This has been taken care of in firmware for the Page 0 SRAM. This firmware is implemented in MAR which in EPLD hosting the necessary logic. However,since accesses to the Boswell or Johnson SRAMs should be rare from the i960, (and since implementation would be difficult) this has NOT been taken care of for the Boswell and Johnson memories. That is, the PROGRAMMER MUST TAKE THIS INTO ACCOUNT when addressing the Boswell and Johnson SRAMs from the i960.
In the next revision of the state machine design, this inconenience will be reviewed and possibly eliminated. This would require 603 work in the little endian mode, thus providing an uniform data alignment and eliminating unnecessary hardware. Also, for the ORCAs to work in conjunction with 603 and i960, this data alignment discrepency would only require extra hardware and careful programming to make correct adjustment. It makes no engineering sense. -- ken
PC603 PROCESSOR ADDRESS SPACE ---------------------------------------------------- Since the 603 is operating in Little Endian mode, the lower order address bits will be changed. (See note. <<
The Register Interface and the Page0 SRAM described above give the i960 and the 603 the means to pass data and have shared memory with each other. However, this is not an efficient means of a semaphore. To realize a handshake protocol between the i960 and the 603, each processor has a dedicated interrupt to each other.
The SMI interrupt is a i960 to 603 signal used so that the i960 may interrupt the 603 to request a service. This is accomplised by enabling the SMI interrupt bit in the Register Interface, causing the 603 to vector to the /SMI interrupt handler. This handler code checks the value in the General Purpose Register to find the type of service requested. The 603 may acknowledge this interrupt by clearing the enable bit itself on the Register Interface.
The LPI interrupt is a 603 to i960 signal used so that the 603 may interrupt the i960 to signal when it has completed a flood service. When the 603 enables this bit, an interrupt signal (which is bussed with the other stream processor cards' signals) is generated to the i960. The i960 in turn polls each State Machine installed to identify which board sent the interrupt. The i960 may then acknowledge the interrupt by clearing the enable bit on the Register Interface.
Ramlogging is a Cheops system-wide means of message-passing between different boards. Here, ramlogging provides a of means message-passing from the State Machine to the P2 board. A RAMLOG consists of a circular queue in memory with a head and tail pointer. When an value is added to the queue by the 603 on the State Machine, the ?head? pointer is advanced. The i960 of the P2 periodically checks the head and tail pointers of the ramlog. If the two pointers do not match, then the i960 pops values off of the circular queue, and then advances the tail pointer. If the 603 fills the entire circular queue and runs out of space, it overwrites the least recent value in the queue.
ORCA to 603 interrupt
The ORCAs need to be able to signal the 603 when it has completed a flood transfer. Both the Boswell and the Johnson ORCA have interrupt signals which are wire ORed to feed the EXTERNAL INTERRUPT pin on the 603. The 603 can then poll the register interface FLEX interrupt store address to identify which ORCA interrupted it.
603 to ORCA interrupt acknowledge
The 603 may acknowledge the above interrupt by asserting the BINT_ACK or JINT_ACK signals which are wired to high order address bits on the 603.
Signals from P2 board for Flood Interface:
----------------------------------------------------
EHubClk
FloodClk = half the frequency of Hubclk, but synchronous to hub Clock
FloodOK(2:0) = Used to signify the start of a transfer
Parameters via the Register I/F -
FloodOK Index - specifies which of the three FloodOK signals to use.
??Flood Delay?? - specifies the number of Hubclk cycles between the assertion of FloodOK
and the beginning of data transfer.
??length/stride??
Typical Flood Control Sequence:
----------------------------------------------------
i960 writes to registers on ORCAs to tell them that it will be receiving a flood transfer,
and specifies which of the FLOODOK(2:0) signals the ORCA should monitor.
When the proper FLOODOK signal goes high, the data transfer will begin within a fixed
number of HubClk cycles. The ORCA must therefore delay 'FloodOK Index' number of HubClk
cycles before counting data.
This section contains information useful in debugging the State Machine as well as a link to a status report on the current state of debugging.
The following are pointers to the EPLD files as of 8/17/96. The garden
copies are considered backups, though they are current. - RYU
Bus controller:
phurther - E:\USERS\STATEMAC\MAXV61\BUSCTLR\V3_3\
garden - /cheops/hdwe/p2/statemch/busctlr/V3/
here is the source file.
Reg Interface:
phurther - E:\USERS\STATEMAC\MAXV61\REGINT\V3\
garden - /cheops/hdwe/p2/statemch/regint/V3/
here is the source file.
Pg0MAR:
phurther - E:\USERS\STATEMAC\MAXV61\PG0MAR\
garden - /cheops/hdwe/p2/statemch/pg0mar/V3/
here is the source file.
The following are pointers to the PAL files as of 8/17/96. -RYU
Boswell/Johnson Memory PALs (Note that the Bos and Jon versions
are identical.)
E15-347 PC - c:\stmchpal\V3\bosmem3.abl
bosmemct.jed
garden - /cheops/hdwe/p2/statemch/busctlr/V3pals/bosmem3.abl
bosmemct.jed
here is the source file.
Counters pal
E15-347 PC - c:\stmchpal\V3\counters.abl
counters.jed
garden - /cheops/hdwe/p2/statemch/busctlr/V3pals/counters.abl
counters.jed
here is the source file.
LB Bus transfer Pal
E15-346 PC - c:\stmchpal\V3\lbbustr.abl
lbbustr.jed
garden - /cheops/hdwe/p2/statemch/busctlr/V3pals/lbbustr.abl
lbbustr.jed
here is the source file.
The original assembly documents live on the Mac in 346 under: Hard disk -> users -> ross ->STMFabDocs STMbom STMAssemblyInstr The updated assembly instructions which should be used for any new State Machine boards are: Hard disk -> users -> ross ->STMFabDocs_current STMbom STMAssemblyInstr
The State Machine has Test Points along the board.
G0,G1,G2,G3 black GND
TP1 blue SYSCLK (SCLK2 on full schematics)
The State Machine has Test pads along the top of the Board (near U17). The first and last ones are labelled S1 and S16 respectively. The following are the names and numbering:
PG2B S1
PC6_ADDR0 S2
PC6_ADDR1 S3
PC6_ADDR2 S4
PC6_ADDR3 S5
PC6_ADDR4 S6
CONFCLK S7
CONFSYNC S8
CONFWR S9
BPRGM* S10
JPRGM* S11
BCONF_DONE S12
JCONF_DONE S13
CONFST S14
STRT S15
PG1B S16
The LEDs are lit when the output enables for the Boswell or Johnson SRAMs are asserted.
Red LED - Boswell SRAM OE (PAGE1)
Green LED - Johnson SRAM OE (PAGE2)
Table 9 : Signal Naming Scheme---------------------------------------------------------------------------------------- | in 603 | @603 | in RegIF | @RegIF | in BCtlr | @BCtlr | in Bos | @Bos | ---------------------------------------------------------------------------------------- | XXXXXX | XXXXXXXX | BINT_AACK | BINT_AACK | XXXXXXXX | XXXXXXXX | ?????? | BINT_AACK | ---------------------------------------------------------------------------------------- | addr_3 | BINTAACK | BINTAACK | BINTAACK | XXXXXXXX | XXXXXXXX | XXXXXX | XXXXXXXXX | ---------------------------------------------------------------------------------------- | XXXXXX | XXXXXXXX | BOS_INT | BOS_INT | XXXXXXXX | XXXXXXXX | INT | BOS_INT | ---------------------------------------------------------------------------------------- | INT_ | INT* | /INT | INT* | XXXXXXXX | XXXXXXXX | XXXXXX | XXXXXXXXX | ---------------------------------------------------------------------------------------- | addr_8 | REGB | PC6addr23 | REGB | addr23 | REGB | XXXXXX | XXXXXXXXX | ---------------------------------------------------------------------------------------- | tt_1 | PC6R/W | PC6R/W | PC6R/W | RR/W | PC6R/W | XXXXXX | XXXXXXXXX | ---------------------------------------------------------------------------------------- | AACK_ | PC6AACK | XXXXXXXXX | XXXXXXXXX | AACK | PC6AACK* | XXXXXX | XXXXXXXXX | ---------------------------------------------------------------------------------------- | BR_ | PC6BR* | XXXXXXXXX | XXXXXXXXX | PBR? | PC6BR* | XXXXXX | XXXXXXXXX | ----------------------------------------------------------------------------------------
The following files are included as functions in busctlr3.tdf. There are other .tdf files in the /cheops/hdwe/p2/statemch/busctlr/V3/subdesigns directory, but they are not included in busctlr3.tdf (figure out why this is).
A B C ------------------------------ 01 | Ain0 | Ain1 | Aout0 | 01 02 | Ain2 | Aout1 | Aout2 | 02 03 | Ain3 | GND | Aout3 | 03 04 | Ain4 | Ain5 | Aout4 | 04 05 | Ain6 | Aout5 | Aout6 | 05 06 | Ain7 | Ain8 | Aout7 | 06 07 | Ain9 | GND | Aout8 | 07 08 | Ain10 | Aout9 | Aout10 | 08 09 | Ain11 | Ain12 | Aout11 | 09 10 | Ain13 | Aout12 | Aout13 | 10 11 | Ain14 | GND | Aout14 | 11 12 | Ain15 | FloodOK0 | Aout15 | 12 13 | Addr0 | | Addr1 | 13 14 | Addr2 | FloodOK1 | Addr3 | 14 15 | Addr4 | GND | Addr5 | 15 16 | Addr6 | EHubClk | Addr7 | 16 17 | Addr8 | | Addr9 | 17 18 | Addr10 | FldClk | Addr11 | 18 19 | Addr12 | GND | Addr13 | 19 20 | Addr14 | FloodOK2 | Addr15 | 20 21 | Bin0 | | Bout0 | 21 22 | Bin1 | Bin2 | Bout1 | 22 23 | Bin3 | GND | Bout2 | 23 24 | Bin4 | Bout3 | Bout4 | 24 25 | Bin5 | Bin6 | Bout5 | 25 26 | Bin7 | Bout6 | Bout7 | 26 27 | Bin8 | GND | Bout8 | 27 28 | Bin9 | Bin10 | Bout9 | 28 29 | Bin11 | Bout10 | Bout11 | 29 30 | Bin12 | Bin13 | Bout12 | 30 31 | Bin14 | GND | Bout13 | 31 32 | Bin15 | Bout14 | Bout15 | 32 ------------------------------
To generate the JEDEC file, the PALs for the State Machine need to be compiled using ABEL4 on the ancient PC in E15-347.
Compile (menu)
|
-----> Compile (command)
View (menu)
|
-----> JEDEC/PROM Fuse File
(This will update the JEDEC file.)
[1] PowerPC603 RISC Microprocessor User's Manual
IBM #MPR603UMU-01
1994
[2] AT&T Field-Programmable Gate Arrays Data Book
AT&T Microelectronics
April 1995
[3] "A Field Programmable Gate Array Based Stream Processor for the
Cheops Imaging System"
Ross Anthony Yu
August 1996