Plotting in Concept

COMPILATION NOTES:
----------------------	
Before compiling, from within Concept, run 'check' command on each page of
design.

To generate a NETLIST, from the BOARD DESIGN menu of SYSLAB, you must go
through each of the following:
	Compile
	Package -> generates NetList
	BOM	-> (Bill of Materials; generates parts list)
o Files of interest for debugging:
	cmplog.dat - 	Is a log file of the compilation.  Gives summary 
			information such as number of errors in pages.
	cmplst.dat -	Lists and explains ERRORs.  This should be generated
			whenever errors arise in compilation; if not COMPERR
			command will generate it.  (See openbook help.)

o Files that comprise a Netlist (i.e. files that outside contractors would
  ask for to do board layout.):
	pstchip.dat	- summary of the chip_prt files for all of the parts
	pstxnet.dat	- the 'extended' netlist.  specifies connections
	pstxprt.dat	- description of parts used.

o Typical compiler errors:
	1) 
		The pin_number assigned needs to be REATTACHed to the actual 
		pin.  (Be sure not to attach to the wire).
	2) From cmplst.dat, an error such as:
	
	>	 ValidLINKER error messages
	>	 --------------------------
	>
	>
	>	 Cadence Design Systems, Inc.  ValidLINKER  02.3 ??-p02
	>	 (C) Copyright 1984,1992 Cadence Design Systems, Inc.
	>
	>
	>	 #1 ERROR(243): Compiler errors in a drawing
	>	    Drawing: "UPD431018LE15".CHIPS_PRT
	>	             No parameters
	>	    Page 1 contains 1 compiler error.

	is due to the newparts library being declared as a library, instead of
	a logic design that uses the part.  Make sure the directory has logic.*
	files and not library.* files.

	3) If the linker has problems locating a certain device library part,
		double check that the DRAWING properties exactly match the
		entry in the partlib.wrk file.

	4) You could run into compiler errors if you have pins whose pin 
	names are numbers. Solution: go change the pin names to alphanumeric.

	5) For some strange reason the parts; GND, VDD, and VCC defined in the
 	Cadence supplied element.lib gives a compiler error code 191. This 
	could be solved by using the parts 5V, 3V, and 0V defined in 
	partlib.wrk. The VCC and VDD bodies in element.lib have an invisible 
	SIZE property which the compiler rejects.   

	6) The compiler rejects a bustap signal name that is not a number 
	within the bit range of the bus. A bustap signame such as RD*, WR* is 
	not allowed by the compiler. 

This is a "fix it yourself" page, located at ${CHEOPS_BASE}/WWW/cadence/index.html