% 6.111 Final Project - Fall 1996 - "PIC-Cam" %
% Kenneth B. Russell <kbrussel@mit.edu> %

INCLUDE "jpeg_ss.inc";
INCLUDE "uart_ss.inc";

% Chip combining the JPEG and UART controller state machines. %

SUBDESIGN JPEG_UART_Ctl
(
	% Inputs %
	/clk			: INPUT;	% 12.2727 MHz (~80ns) clock (LLC) %
	
	% For UART Controller %
	uc_reset		: INPUT;
	uc_init			: INPUT;
	uc_send			: INPUT;
	uc_hi_sel		: INPUT;
	uc_db[8..1]		: BIDIR;	% UART data bus %
	/uc_txrdy		: INPUT;	% /Ready To Transmit %
	/uc_rts			: INPUT;	% /Request To Send %
	
	% For JPEG Controller %
	jc_reset		: INPUT;
	jc_init			: INPUT;
	jc_go			: INPUT;
	
	% Outputs %
	% From UART Controller: %
	%  - to main FSM %
	uc_busy			: OUTPUT;
	%  - to UART %
	uc_addr[3..1]	: OUTPUT;
	uc_mr			: OUTPUT;	% Master Reset %
	/uc_cs			: OUTPUT;
	/uc_wr			: OUTPUT;
	%  - to UART's bus transceivers %
	uc_clkab		: OUTPUT;
	/uc_oelo		: OUTPUT;
	/uc_oehi		: OUTPUT;
	% From JPEG Controller: %
	%  - to main FSM %
	jc_busy			: OUTPUT;
	%  - to ZR36050 %
	jc_clken		: OUTPUT;
	/jc_cs			: OUTPUT;
	/jc_wr			: OUTPUT;
	/jc_reset_zr	: OUTPUT;
	%  - to 28F256As %
	jc_addr[10..1]	: OUTPUT;
	/jc_oe			: OUTPUT;
)
VARIABLE
	jpss			: jpeg_ss;
	ucss			: uart_ss;
BEGIN
	% Set up the JPEG controller first %
	% Inputs: %
	jpss./clk 		= /clk;
	jpss.reset_ss	= jc_reset;
	jpss.init		= jc_init;
	jpss.go			= jc_go;
	% Outputs: %
	jc_busy			= jpss.busy;
	jc_clken		= jpss.clken;
	/jc_cs 			= jpss./cs;
	/jc_wr			= jpss./wr;
	/jc_reset_zr	= jpss./reset;
	jc_addr[]		= jpss.addr[];
	/jc_oe			= jpss./oe;
	
	% Now set up the UART controller %
	% Inputs: (ignoring BIDIR inputs for the moment) %
	ucss./clk		= /clk;
	ucss.reset		= uc_reset;
	ucss.init_uart	= uc_init;
	ucss.send_byte	= uc_send;
	ucss.hi_sel		= uc_hi_sel;
	ucss./txrdy		= DFF(/uc_txrdy, /clk, VCC, VCC);	% Registered input %
	ucss./rts		= /uc_rts;
	% Outputs: (ignoring BIDIR outputs for the moment) %
	uc_busy			= ucss.busy;
	uc_addr[]		= ucss.addr[];
	uc_mr			= ucss.reset_uart;
	/uc_wr			= ucss./wr;
	/uc_cs			= ucss./cs;
	uc_clkab		= ucss.clkab;
	/uc_oelo		= ucss./oelo;
	/uc_oehi		= ucss./oehi;
	% Bidir ports %
	uc_db8			= TRI(ucss.db_out8, ucss.oedb);
	uc_db7			= TRI(ucss.db_out7, ucss.oedb);
	uc_db6			= TRI(ucss.db_out6, ucss.oedb);
	uc_db5			= TRI(ucss.db_out5, ucss.oedb);
	uc_db4			= TRI(ucss.db_out4, ucss.oedb);
	uc_db3			= TRI(ucss.db_out3, ucss.oedb);
	uc_db2			= TRI(ucss.db_out2, ucss.oedb);
	uc_db1			= TRI(ucss.db_out1, ucss.oedb);
	ucss.db_in[]	= uc_db[];
END;